Method for operating a non-volatile memory cell arrangement

ABSTRACT

In order to increase the storage density, in a memory cell arrangement having MOS transistors as memory cells which has as gate dielectric, a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the silicon oxide layers each having a thickness of at least 3 nm, the information is stored using multi-value logic with up to 2 6  values. In this case, use is made of the fact that these memory cells have a time period greater than 1000 years for data retention and their threshold voltage has a very small drift.

BACKGROUND OF THE INVENTION

For the permanent storage of data, nonvolatile EEPROM cells are usuallyused. Various technologies have been proposed for realising EEPROM cells(see, for example, Lai et al., IEDM Tech. Dig., 1986, pages 580-583).

On the one hand, specific MOS transistors are used as memory cells inthe so-called SONOS or MNOS cells. The MOS transistor comprises a gatedielectric comprising at least one silicon oxide layer underneath thegate electrode and a silicon oxide layer between the silicon nitridelayer and the channel region. In order to store information, chargecarriers are stored in the silicon nitride layer.

The silicon oxide layer has a maximum thickness of 2.2 mm in SONOScells. The silicon nitride layer usually has a thickness of about 10 nmin modern SONOS memories. A further silicon oxide layer, having athickness of 3 to 4 nm, is usually provided between the silicon nitridelayer and the gate electrode. These nonvolatile memory cells can bewritten to and erased electrically. During a writing operation, avoltage is applied to the gate electrode such that charge carrierstunnel from the substrate through the silicon oxide layer having amaximum thickness of 2.2 nm into the silicon nitride layer. For erasure,the gate electrode is connected up in such a way that the chargecarriers stored in the silicon nitride layer tunnel through the siliconoxide layer having a thickness of 2 nm into the channel region andcharge carriers of the opposite conductivity type tunnel from thechannel region through the silicon oxide layer into the silicon nitridelayer.

SONOS cells having a time period of ≦10 years for data retention. Thistime period is too short for many applications, for example for thestorage of data in computers.

EEPROM cells with floating gate are used as an alternative to the SONOScells. These EEPROM cells are suitable for applications in which longertime periods are required for data retention. In these memory cells, afloating gate electrode, which is completely surrounded by dielectricmaterial, is arranged between a control gate electrode and the channelregion of the MOS transistor. The information is stored in the form ofcharge carriers on the floating gate electrode. These memory cells,which are also referred to as FLOTOX cells, can be written to and erasedelectrically. For this purpose, the control gate electrode is connectedto a potential such that charge carriers flow from the channel regiononto the floating gate electrode (writing) or charge carriers flow fromthe floating gate electrode into the channel region (erasure). TheseFLOTOX cells have time periods of < than 150 years for data retention.

However, they have a complicated structure in comparison with the SONOScells. Furthermore, FLOTOX cells require more space than SONOS cellssince the control gate electrode must laterally overlap the floatinggate electrode. Finally, the so-called radiation hardness of FLOTOXcells is limited. Radiation hardness refers to the insensitivity of thestored charge to external radiation sources and/or electromagneticfields.

In order to increase the storage density in FLOTOX cells, it has beenproposed (see, for example, Lai et al., IEDM Tech. Dig., 1986, pages580-583) to store information in the sense of multi-value logic. In thiscase, more than 3 logic values are stored by unambiguously assigning athreshold voltage value of the MOS transistor to each logic value. Inthe course of programming, the different threshold voltage values areset, in dependence on the logic value to be stored, by injectingdifferent quantities of charge.

SUMMARY OF THE INVENTION

The invention is based on the problem of specifying a method foroperating a memory cell arrangement in which an increased storagedensity is achieved compared with the prior art and in which a timeperiod of at least 150 years for data retention is achieved.

In general terms the present invention is a method for operating amemory cell arrangement. The memory cells used are MOS transistorshaving, as gate dielectric, a dielectric triple layer having a siliconoxide layer, a silicon nitride layer and a second silicon oxide layer,the first silicon oxide layer and the second silicon oxide layer eachhaving a thickness of at least 3 nm. Multi-value logic with more thantwo logic values is used in order to store information. In order towrite the logic values to one of the memory cells, a respective quantityof charge assigned to the logic value is applied to the gate dielectricby Fowler-Nordheim tunneling and is stored in the gate dielectric, whichquantity of charge effects a threshold voltage level of the MOStransistor which is assigned to the logic value.

Advantageous developments of the present invention are as follows.

The amount separating neighboring threshold voltage levels increase asthe threshold voltage level increases.

The difference between the thickness of the first silicon oxide layerand the second silicon oxide layer lies in the range between 0.5 nm and1 nm.

The smaller of the thicknesses of the first silicon oxide layer and ofthe second silicon oxide layer lies in the range between 3 and 6 nm.

The silicon nitride layer has a thickness of at least 5 nm.

The MOS transistor in each case has a gate electrode made of n-dopedsilicon. Furthermore, multi-value logic with 2^(n) values is used, wheren is between 2 and 6.

The difference between the thicknesses of the first silicon oxide layerand the second silicon oxide layer lies in the range between 0.5 nm and1 nm. The smaller of the thicknesses of the first silicon oxide layerand of the second silicon oxide layer lies in the range between 3.2 and4 nm. The silicon nitride layer has a thickness of at least 5 nm. TheMOS transistor in each case has a gate electrode made of p⁺ -dopedsilicon. The p⁺ -doped silicon in the gate electrode has a dopantconcentration of at least 1×10²⁰ cm⁻³. The multi-value logic with 2^(n)values is used, where n is between 2 and 3.

In the method according to the invention, a memory cell arrangement isused which comprises, as memory cells, in each case a MOS transistorwith source region, channel region, drain region, gate dielectric andgate electrode, the gate dielectric of which transistor is in the formof a dielectric triple layer. The dielectric triple layer comprises afirst silicon oxide layer, a silicon nitride layer and a second siliconoxide layer. The silicon nitride layer is arranged between the twosilicon oxide layers. The first silicon oxide layers and the secondsilicon oxide layer each have a thickness of at least 3 nm.

The memory cell used in the method according to the invention differsfrom conventional SONOS cells by the fact that the first silicon oxidelayer, which is arranged between the channel region of the MOStransistor and the silicon nitride layer, has a thickness of at least 3nm. This thickness is at most 2.2 nm in conventional SONOS cells.

The method according to the invention makes use the insight that inconventional SONOS cells, the charge transport through the first siliconoxide layer takes place primarily. by means of direct tunneling andmodified Fowler-Nordheim tunneling. The probability for direct tunnelingand modified Fowler-Nordheim tunneling and thus the current intensityfor the charge transport by these tunneling mechanisms depend primarilyon the thickness of the tunneling barrier, that is to say the thicknessof the first silicon oxide layer, and on the electric field. Since thefirst silicon oxide layer has a maximum thickness of 2.2 nm and thesecond silicon oxide layer a thickness of 3 to 4 nm is conventionalSONOS cells, the current due to direct tunneling through the firstsilicon oxide layer is always predominant given electric fields of below10 MV/cm. The information is both written and erased by means of thisdirect tunneling current, by virtue of the gate electrode beingconnected up correspondingly.

In conventional SONOS cells, even without the gate electrode beingconnected up, a tunneling current ascribed to direct tunneling flowsthrough the first silicon oxide layer from the silicon nitride layer tothe channel region. It has been ascertained that this direct tunnelingcurrent determines the time period for data retention.

Moreover, the method according to the invention makes use of the factthat the probability for direct tunneling greatly decreases as thethickness of the first silicon oxide layer increases, and becomes verylow given a thickness of at least 3 nm. At a thickness of 3 nm, theprobability for direct tunneling is less than in the case of 2 nmapproximately by a factor of 10⁶.

Since, in the memory cell which is used in the method according to theinvention, the first silicon oxide layer and the second silicon oxidelayer each have a thickness of at least 3 nm, charge carrier transportfrom the silicon nitride layer to the gate electrode or to the channelregion as a result of direct tunneling is largely avoided in this memorycell. That is to say that charge stored in the silicon nitride layer ispreserved in a practically unlimited manner. The time period for dataretention is therefore considerably longer in this memory cell than inconventional SONOS cells. It is >1000 years instead of 10 years in thecase of conventional SONOS cells.

It has been observed that the threshold voltage of the MOS transistorsin the memory cells used in the method according to the invention driftstoward higher values with time. This profile of the threshold voltageshows that there is no loss of charge stored in the silicon nitridelayer. What occurs, rather, is a migration of the charged stored in thesilicon nitride layer in the direction of the substrate.

Since the thicknesses of the first silicon oxide layer and of the secondsilicon oxide layer in the memory cell used in the method according tothe invention are at least 3 nm in each case, the probability for directtunneling of charge carriers through the two silicon oxide layers isvery small. Charge carrier transport through the first silicon oxidelayer and/or second silicon oxide layer takes place only as a result ofFowler-Nordheim tunneling. The current intensity of the charge carriertransport as a result of Fowler-Nordheim tunneling depends only on thestrength of the applied electric field. It is not explicitly dependenton the thickness of the tunneling barrier, that is to say that thicknessof the first silicon oxide layer and/or second silicon oxide layer.

In the method according to the invention, different threshold voltagelevels of the MOS transistor are assigned to different logic values.Owing to the long time period for data retention, these thresholdvoltage levels are very stable and, therefore, it is possible to providea large number of threshold voltage levels per volt.

The threshold voltage levels can be separated from one another byidentical of different amounts. Since the temporal drift of thethreshold voltage levels is greater for larger threshold voltage levelsthan for smaller ones, it is advantageous to define the thresholdvoltage levels such that the amount separating neighboring thresholdvoltage levels increases as the threshold voltage level increases.

According to one embodiment, the memory cell has a gate electrode madeof n-doped silicon, metal or a metal silicide. In this memory cell, theFowler-Nordheim tunneling of electrons dominates the charge carriertransport irrespective of the polarity of the applied field. That is tosay that not only when a positive voltage is applied but also when anegative voltage is applied to the gate electrode. Fowler-Nordheimtunneling of electrons into the silicon nitride layer occurs. If apositive voltage is applied to the gate electrode, then electrons tunnelfrom the channel region through the first silicon oxide layer into thesilicon nitride layer. If, on the other hand, a negative voltage isapplied to the gate electrode, then electrons tunnel by Fowler-Nordheimtunneling from the gate electrode through the second silicon oxide layerinto the silicon nitride layer.

Since, in this memory cell, electrons are transported into the siliconnitride layer as a result of Fowler-Nordheim tunneling irrespective ofthe polarity applied to the gate electrode, electrons cannot be removedagain once they have been transported into the silicon nitride layer.The memory cell therefore has a very long time period for dataretention. The threshold voltage levels are so stable over time that itis possible to provide 64 threshold voltage levels in a voltage windowof 4 volts.

In this memory cell, the difference between the thicknesses of the firstsilicon oxide layer and of the second silicon oxide layer preferablylies in the range between 0.5 nm and 1 nm. The smaller of thethicknesses of the first silicon oxide layer and of the second siliconoxide layer lies in the range between 3 nm and 6 nm. The thickness ofthe silicon nitride layer is at least 5 nm. In another embodiment of theinvention, a memory cell is used which has a gate electrode made of p⁺-doped silicon. In comparison with n-doped silicon or metal, which isused as gate electrode in the first embodiment, in the ideal case the p⁺-type doping reduces the occupation probability of electronic states inthe gate electrode approximately by a factor of 10²⁰. Therefore,information stored in the memory cell can be electrically erased. Noelectrons can tunnel from the gate electrode into the silicon nitridelayer during the erase operation, owing to the reduced occupationprobability of electronic states. The erase operation of the memory cellaccording to the invention therefore takes place by way of holestunneling from the channel region through the first silicon oxide layerinto the silicon nitride layer and by electrons tunneling from thesilicon nitride layer into the channel region. In the case of memorycells having gate electrodes which are rich in electrons, electronsadditionally tunnel from the gate electrode into the silicon nitridelayer, which likewise have to be neutralized during the erase operation.This electron current is suppressed in the memory cell used here by thefact that the number of electrons in the gate electrode is reduced bythe use of p⁺ -doped silicon. Compared with memory cells having gateelectrodes which are rich in electrons, the time for the erase operationis reduced by a factor of approximately 10⁵ in this memory cell.

However, the loss of charge from the silicon nitride layer as a resultof direct tunneling in this case is a plurality of orders of magnitudehigher than compared with memory cells having gate electrodes which arerich in electrons. For this reason, it is only possible to provide asmaller number of threshold voltage levels per volt. Given erase timesof the order of magnitude of 1 second, 4 to 8 threshold voltage levelsare possible in a window of 4 volts.

With regard to erase times of less than 30 seconds, it is advantageousin this memory cell to give the first silicon oxide layer and the secondsilicon oxide layer a thickness of between 3.2 nm and 4 nm.

Memory cell arrangements which, as is generally customary, have amultiplicity of identical memory cells in the form of a matrix can beoperated by the method according to the invention.

The MOS transistors in the memory cells can be designed both as planarand as vertical MOS transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings, in the several Figures of which like referencenumerals identify like elements, and in which:

FIG. 1 shows a memory cell with a planar MOS transistor having a gateelectrode made of n-doped silicon.

FIG. 2 shows a memory cell with a planar MOS transistor having a gateelectrode made of p⁺ -doped silicon.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A source region 2 and a drain region 3, which are n-doped, for example,are provided in a substrate 1 comprising monocrystalline silicon atleast in the region of a memory cell (see FIG. 1). A channel region 4 isarranged between the source region 2 and the drain region 3. Sourceregion 2, channel region 4 and drain region 3 are, for example, arrangednext to one another on the surface of the substrate 1. As analternative, they may also be arranged in the form of a vertical layersequence.

Arranged above the channel region 4 is a dielectric triple layer, whichcomprises a first SiO₂ layer 51, an Si₃ N₄ layer 52 and a second SiO₂layer 53. The first SiO₂ layer 51 is arranged on the surface of thechannel region 4 and has a thickness of 3 to 6 nm, preferably 5 nm. TheSi₃ N₄ layer 52 is arranged on the surface of the first SiO₂ layer 51.It has a thickness of at least 5 nm, preferably 8 nm. The second SiO₂layer 53 is arranged on the surface of the Si₃ N₄ layer 52 and itsthickness is 0.5 to 1 nm greater than the thickness of the first SiO₂layer 52, that is to say it lies in the range between 3.5 and 6.5 nm,and is preferably 4.5 nm.

A gate electrode 6 made of n⁺ -doped polysilicon, for example, isarranged on the surface of the dielectric triple layer 5. The gateelectrode 6 has a thickness of 200 nm, for example, and a dopantconcentration of 10²¹ cm⁻³, for example. Alternatively, the gateelectrode 6 can also be formed from metal, for example aluminum, or ametal silicide, for example TiSi₂.

In order to operate a memory cell arrangement having a multiplicity ofidentical memory cells of the kind illustrated in FIG. 1, theinformation is stored in the sense of multi-value logic, for examplewith 2⁵ =32 values. For this purpose, 32 threshold voltage levels aredefined in a threshold voltage window of 3.2 volts, for example. Thefollowing holds true, for example:

    ______________________________________                                        Number of the threshold                                                                       Threshold voltage level                                       voltage level   (mV)                                                          ______________________________________                                        0               400                                                           1               442                                                           2               488                                                           3               538                                                           4               592                                                           5               650                                                           6               712                                                           7               778                                                           8               848                                                           9               922                                                           10              1000                                                          11              1082                                                          12              1168                                                          13              1258                                                          14              1352                                                          15              1450                                                          16              1552                                                          17              1658                                                          18              1768                                                          19              1882                                                          20              2000                                                          21              2122                                                          22              2248                                                          23              2378                                                          24              2512                                                          25              2650                                                          26              2792                                                          27              2938                                                          28              3088                                                          29              3242                                                          30              3400                                                          31              3562                                                          ______________________________________                                    

The amount separating neighboring threshold voltage levels increases asthe threshold voltage level increases. In the case of the smallestthreshold voltage levels around 0.4 volt, said amount separatingneighboring threshold voltage levels is 0.04 volt; in the case ofthreshold voltage levels around 3.4 volts, said amount separatingneighboring threshold voltage levels is 0.15 volt. The temporal drift ofthe threshold voltage level over 10 years amounts to 25 mV given aninitial threshold voltage level of 2 volts, and 42 mV given an initialthreshold voltage level of 3.5 volts.

In order to write in the information, voltage levels between 11.5 voltsand 15.5 volts are applied to the gate electrode given a writing time of1 ms.

In order to read out the information, the threshold voltage level of thememory cell can be evaluated, on the one hand. On the other hand, thedependence of the current flowing through the transistor on a controlvoltage applied to the gate electrode can be evaluated.

A source region 2' and a drain region 3', which are n-doped, forexample, are provided in a substrate 1' comprising monocrystallinesilicon at least in the region of a memory cell (see FIG. 2). A channelregion 4' is arranged between the source region 2' and the drain region3'. Source region 2', channel region 4' and drain region 3' are, forexample, arranged next to one another on the surface of the substrate1'. As an alternative, they may also be arranged as a vertical layersequence.

Arranged above the channel region 4' is a dielectric triple layer, whichcomprises a first SiO₂ layer 51', an Si₃ N₄ layer 52' and a second SiO₂layer 53'. The first SiO₂ layer 51' is arranged on the surface of thechannel region 4' and has a thickness of 3.2 to 4 nm, preferably 3.5 nm.The Si₃ N₄ layer 52' is arranged on the surface of the first SiO₂ layer51', and it has a thickness of at least 5 nm, preferably 8 nm. Thesecond SiO₂ layer 53' is arranged on the surface of the Si₃ N₄ layer52', and its thickness lies in the range between 3.5 and 6.5 nm, and ispreferably 4.5 nm.

A gate electrode 6' made of p⁺ -doped polysilicon, for example, isarranged on the surface of the dielectric triple layer 5'. The gateelectrode 6' has a thickness of 200 nm, for example, and a dopantconcentration of 5×10²⁰ cm⁻³, for example.

In order to operate a memory cell arrangement having a multiplicity ofidentical memory cells of the kind illustrated in FIG. 2, theinformation is stored in the sense of multi-value logic, for example 2²=4 values. For this purpose, 4 threshold voltage levels are defined in athreshold voltage window of 4 volts, for example. The following holdstrue, for example:

    ______________________________________                                        Number of the thresh-                                                                        Threshold voltage                                                                         Temporal drift                                     hold voltage level                                                                           level (volts)                                                                             in 10 years (mV)                                   ______________________________________                                        0              0.0         +50                                                1              1.0                                                            100                                                                           2              2.0                                                            400                                                                           3              3.5                                                            1000                                                                          ______________________________________                                    

The amount separating neighboring threshold voltage levels increases asthe threshold voltage level becomes increasingly removed from thethreshold voltage value of the MOS transistor in the absence of anycharge stored in the silicon nitride layer. In the case of the thresholdvoltage levels being removed from the threshold voltage value of the MOStransistor in the absence of any charge stored in the silicon nitridelayer by the smallest amounts around 0.5 volt, said amount separatingneighboring threshold voltage levels is 1.0 volt; in the case of thethreshold voltage levels being removed from the threshold voltage valueof the MOS transistor in the absence of any charge stored in the siliconnitride layer by amounts around 3 volts, said amount separatingneighboring threshold voltage levels is 1.5 volts. The temporal drift ofthe threshold voltage level over 10 years amounts to -1000 mV given aninitial threshold voltage level of 3.5 volts and 50 mV given an initialthreshold voltage level of 0 volts.

In order to write the information to a memory cell in the initial statewith a writing time of 1 ms, voltage levels between +10 volts and +14volts are applied to the gate electrode.

In order to read out the information, the threshold voltage level of thememory cell can be evaluated, on the one hand. On the other hand, thedependence of the current flowing through the transistor on a controlvoltage applied to the gate electrode can be evaluated.

The invention is not limited to the particular details of the methoddepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described method withoutdeparting from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrated and not in alimiting sense.

What is claimed is:
 1. A method for operating a memory cell arrangement,comprising the steps of:providing memory cells having MOS transistors;providing said MOS transistors with a gate dielectric including adielectric triple layer having a first silicon oxide layer, a siliconnitride layer and a second silicon oxide layer; providing the firstsilicon oxide layer and the second silicon oxide layer each with athickness of at least 3 nm; using multi-value logic with more than twologic values to store information; applying a respective quantity ofcharge assigned to the respective logic value to the gate dielectric byFowler-Nordheim tunneling for writing a respective logic value of themore than two logic values to one of the memory cells; and storing therespective quantity of charge in the gate dielectric, said quantity ofcharge effects a threshold voltage level of the MOS transistor which isassigned to the respective logic value.
 2. The method as claimed inclaim 1, further comprising the step of:increasing an amount separatingneighboring threshold voltage levels as the threshold voltage levelincreases.
 3. The method as claimed in claim 1,wherein a differencebetween thicknesses of the first silicon oxide layer and the secondsilicon oxide layer lies in a range between 0.5 nm and 1 nm, wherein asmaller of the thicknesses of the first silicon oxide layer and of thesecond silicon oxide layer lies in a range between 3 nm and 6 nm,wherein the silicon nitride layer has a thickness of at least 5 nm, andwherein each of the MOS transistors has a gate electrode made of n-dopedsilicon.
 4. The method as claimed in claim 3, further comprising thestep of:using multi-value logic with 2n values, where n is between 2 and6.
 5. The method as claimed in claim 1,wherein a difference betweenthicknesses of the first silicon oxide layer and the second siliconoxide layer lies in a range between 0.5 nm and 1 nm, wherein a smallerof the thicknesses of the first silicon oxide layer and of the secondsilicon oxide layer lies in a range between 3.2 and 4 nm, wherein thesilicon nitride layer has a thickness of at least 5 nm, and wherein eachof the MOS transistors has a gate electrode made of p⁺ -doped silicon.6. The method as claimed in claim 5, wherein p⁺ -doped silicon in thegate electrode has a dopant concentration of at least 1×10²⁰ cm⁻³. 7.The method as claimed in claim 5, further comprising the step of:usingmulti-value logic with 2n values, where n is between 2 and 3.